The present invention generally relates to clock generators for capturing picture-in-picture (PIP) images for video signals. More particularly, the present invention relates to a pseudo line locked clock generator for capturing PIP images for both standard and non-standard video signals.
In generating a PIP television image, it is standard to use a "write" clock for capturing the TV images from transmitted signals. The write clock is used to control the analog/digital conversion sample rate as well as to control the writing of the A/D converted signals into the addresses of a memory. In addition, the write clock controls the incoming data sequencing and compression of chrominance data. Once the data is stored at desired addresses in memory, a separate "read" clock is utilized to read the PIP date into the video data stream being sent to the television. The read clock controls the reading of digital signals from the memory as well as the conversion rate of the D/A converter. In addition, the read clock controls the outgoing data sequencing and expansion of the compressed chrominance data.
Because the video signal being captured for PIP display is typically independent of the main video signal which is to be displayed, the PIP write and read clocks are typically asynchronous. The two separate clocks are typically generated via the use of gated oscillators, line locked phase locked loop (PLL) circuits, or burst locked PLL circuits. Regardless of how generated, the use of two separate clocks has various drawbacks. Gated oscillator clocks often result in frequency instability resulting in the requirement that the PIP control integrated circuit must be designed to operate with the clock being off during part of each horizontal line. The line locked PLL clock, on the other hand, is stable, but is expensive to implement and is subject to frequency jitter. The burst locked PLL clock is also expensive to implement and does not operate well with non-standard signals such as might be generated by a VCR.